/[MITgcm]/MITgcm/eesupp/src/barrier.F
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revision 1.4 by cnh, Tue Sep 29 18:50:56 1998 UTC revision 1.6 by adcroft, Tue May 18 17:39:21 1999 UTC
# Line 3  C $Header$ Line 3  C $Header$
3  #include "CPP_EEOPTIONS.h"  #include "CPP_EEOPTIONS.h"
4    
5        SUBROUTINE BARRIER_INIT        SUBROUTINE BARRIER_INIT
6          IMPLICIT NONE
7    
8  #include "SIZE.h"  #include "SIZE.h"
9  #include "EEPARAMS.h"  #include "EEPARAMS.h"
# Line 46  C     | coherency over process caches an Line 47  C     | coherency over process caches an
47  C     | Also we have to be a bit careful regarding sequential    |  C     | Also we have to be a bit careful regarding sequential    |
48  C     | consistency - or lack of it. At the moment the code      |  C     | consistency - or lack of it. At the moment the code      |
49  C     | assumes a total store order memory model, which some     |  C     | assumes a total store order memory model, which some     |
50  C     | machines don't have! However, I have yet to find a       |  C     | machines do not have! However, I have yet to find a      |
51  C     | problem with this I think because the tolerances in      |  C     | problem with this I think because the tolerances in      |
52  C     | terms of memory ordering i.e. a little bit of reordering |  C     | terms of memory ordering i.e. a little bit of reordering |
53  C     | probably won't break the barrier mechanism!              |  C     | probably will not break the barrier mechanism!           |
54  C     | On non-cache coherent systems e.g. T3E we need to use    |  C     | On non-cache coherent systems e.g. T3E we need to use    |
55  C     | a library function to do barriers.                       |  C     | a library function to do barriers.                       |
56  C     | Note - The PANIC tests can be removed for working code   |  C     | Note - The PANIC tests can be removed for working code   |
# Line 85  CcnhDebugEnds Line 86  CcnhDebugEnds
86  C--   Check that thread number is expected range  C--   Check that thread number is expected range
87        IF ( myThid .LT. 1 .OR. myThid .GT. nThreads ) THEN        IF ( myThid .LT. 1 .OR. myThid .GT. nThreads ) THEN
88         WRITE(0,*) '!!!!!!! PANIC !!!!!!! CATASTROPHIC ERROR'         WRITE(0,*) '!!!!!!! PANIC !!!!!!! CATASTROPHIC ERROR'
89         WRITE(0,*) '!!!!!!! PANIC !!!!!!! in S/R BARRIER  myThid = ', myThid, ' nThreads = ', nThreads         WRITE(0,*) '!!!!!!! PANIC !!!!!!! in S/R BARRIER  myThid = ',
90         &  myThid, ' nThreads = ', nThreads
91         STOP 'ABNROMAL END: S/R BARRIER'         STOP 'ABNROMAL END: S/R BARRIER'
92        ENDIF        ENDIF
93    
94  C--   When every threads key1 is valid thread 1 will open door1.  C--   When every threads key1 is valid thread 1 will open door1.
95        IF ( key1(1,myThid) .EQ. VALID ) THEN        IF ( key1(1,myThid) .EQ. VALID ) THEN
96         WRITE(0,*) '!!!!!!! PANIC !!!!!!! CATASTROPHIC ERROR'         WRITE(0,*) '!!!!!!! PANIC !!!!!!! CATASTROPHIC ERROR'
97         WRITE(0,*) '!!!!!!! PANIC !!!!!!! in S/R BARRIER  myThid = ', myThid, ' key1 already validated'         WRITE(0,*) '!!!!!!! PANIC !!!!!!! in S/R BARRIER  myThid = ',
98         &  myThid, ' key1 already validated'
99         STOP 'ABNROMAL END: S/R BARRIER'         STOP 'ABNROMAL END: S/R BARRIER'
100        ENDIF        ENDIF
101        key1(1,myThid) = VALID        key1(1,myThid) = VALID
# Line 131  C--   door3 because they have to go thro Line 134  C--   door3 because they have to go thro
134  C--   When every threads key2 is valid thread 1 will open door2.  C--   When every threads key2 is valid thread 1 will open door2.
135  C     Notes  C     Notes
136  C     =====  C     =====
 C      I don't understand memory ordering and sequential consistency.  
137  C     I think that to work with any memory model ( i.e. relaxed,  C     I think that to work with any memory model ( i.e. relaxed,
138  C     partial store, total store) the variables key1, key2 and key3  C     partial store, total store) the variables key1, key2 and key3
139  C     might need to be set to invalid by thread 1.  C     might need to be set to invalid by thread 1.
140  C      C    
141        IF ( key2(1,myThid) .EQ. VALID ) THEN        IF ( key2(1,myThid) .EQ. VALID ) THEN
142         WRITE(0,*) '!!!!!!! PANIC !!!!!!! CATASTROPHIC ERROR'         WRITE(0,*) '!!!!!!! PANIC !!!!!!! CATASTROPHIC ERROR'
143         WRITE(0,*) '!!!!!!! PANIC !!!!!!! in S/R BARRIER  myThid = ', myThid, ' key2 already validated'         WRITE(0,*) '!!!!!!! PANIC !!!!!!! in S/R BARRIER  myThid = ',
144         &  myThid, ' key2 already validated'
145         STOP 'ABNROMAL END: S/R BARRIER'         STOP 'ABNROMAL END: S/R BARRIER'
146        ENDIF        ENDIF
147        key2(1,myThid) = VALID        key2(1,myThid) = VALID
# Line 173  C--   door1 because they have to go thro Line 176  C--   door1 because they have to go thro
176  C--   When every threads key3 is valid thread 1 will open door3.  C--   When every threads key3 is valid thread 1 will open door3.
177        IF ( key3(1,myThid) .EQ. VALID ) THEN        IF ( key3(1,myThid) .EQ. VALID ) THEN
178         WRITE(0,*) '!!!!!!! PANIC !!!!!!! CATASTROPHIC ERROR'         WRITE(0,*) '!!!!!!! PANIC !!!!!!! CATASTROPHIC ERROR'
179         WRITE(0,*) '!!!!!!! PANIC !!!!!!! in S/R BARRIER  myThid = ', myThid, ' key3 already validated'         WRITE(0,*) '!!!!!!! PANIC !!!!!!! in S/R BARRIER  myThid = ',
180         &  myThid, ' key3 already validated'
181         STOP 'ABNROMAL END: S/R BARRIER'         STOP 'ABNROMAL END: S/R BARRIER'
182        ENDIF        ENDIF
183        key3(1,myThid) = VALID        key3(1,myThid) = VALID
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